Intel Arrow Lake CPUs to Use TSMC’s 3nm Node & May Not Feature Hyperthreading

The rumor mill is running once more and we have more information regarding Intel’s Arrow Lake CPUs. Arrow Lake is the successor to Meteor Lake and was supposed to be the 15th Generation of Intel Core CPUs. At least, before the naming change took place.

Allegedly, Intel is planning to drop its own Intel 20A process for Arrow Lake. Furthermore, it is probable that hyperthreading or SMT may be disabled in Arrow Lake.

TSMC to The Rescue

Hardware leaker xinoassassin1, in a now-deleted tweet, pointed out that Intel is resorting to TSMC for Arrow Lake. More specifically, the Arrow Lake-H series of mobile SKUs will feature a compute tile based on Intel 20A. For the unaware, the Compute Tile is a chiplet that hosts the performance/efficient cores alongside the respective SRAM cache(s).

Since Intel is aiming at scalability, if ARL-H features a Compute Tile based on Intel 20A, the same could apply to ARL-S. (ARL-S = Arrow Lake for Desktop)

As for the unnamed ‘external process’, the same leaker clarifies and names TSMC’s N3B node as the candidate. We should remind users that Intel, after restructuring its foundry division, considers TSMC’s 3nm to be on-par with Intel 20A.

Most likely, since team blue is seeing a huge paradigm shift with the incorporation of new and innovating technologies such as RibbonFET and PowerVia, using this node for a large-scale operation will not be viable.

This also shows a huge advantage of Intel’s Foveros design since team blue can easily switch to TSMC or Samsung, should things go south. Designing Arrow Lake and even Meteor Lake on Foveros gives Intel some breathing space. This in turn helps consumers since these products do not solely rely on Intel’s own manufacturing abilities as Chipzilla can make do with TSMC’s silicon.

Things becomes more apparent since ‘Golden Pig Upgrade Pack‘, a very reliable leaker has also cleared up some misconception. The leaker has completely cut out Intel’s 20A node which leads us to believe that Arrow Lake may only use Intel 3 and TSMC N3B. Though once again, this is simply speculation and things can turn around pretty quickly (for the better), considering this is Intel we’re talking about.

No Hyperthreading

Hyperthreading is a key feature in modern day processors. Put simply, hyperthreading divides a physical core into two logical cores. This allows the Operating System to consider the single core as two logical cores, enabling more efficient scheduling. Hyperthreading has played a key role in the survival of quad-core and even hexacore processors since modern AAA titles need 6-8 threads at the very least.

Hyperthreading, on paper, does not become as important when we reach core counts in the double digits. There are simply too many cores and even one logical core per a physical core can do the job. And since Intel is keen on increasing core counts with efficiency cores, the reliance on hyperthreading has seemed to decrease.

Efficient cores are small and can run tasks in parallel, effectively acting as threads or logical cores. Likewise, the same leaker mentions that LNC or Lion Cove may not support SMT (Hyper-threading). LNC is the codename for Arrow Lake’s performance cores. Remember, the leaker used the word ‘Maybe‘ so take this with a grain of salt.

Apparently, Intel removed the support for SMT in its supported technologies list for LNC. The leaker clarifies that this may only be disabled on Lunar Lake and Arrow Lake.

Wild_C joined in the action and gave us some insight regarding this leak. To keep things short, there is a trade-off between enabling SMT and opting for more efficient cores. This is just a rumor but enabling SMT for 8 Performance Cores is less efficient than simply adding 2 E-Core clusters (8 E-Cores).

While this is strange for many, Intel was the first to introduce SMT and they could be the first to stop using their own tech. This change reminds us of the good old days of Intel’s 9th Generation i3, i5 and i7 SKUs. Despite not being that old, these CPUs can hit severe bottlenecks due to the lack of SMT. In any case, this is just a rumor but indeed, an interesting concept.

Source: xinoassassin1, Golden Pig Upgrade Pack