The gigantic ceremony for a new 3-nanometer chip production facility in Taiwan was staged today by the Taiwan Semiconductor Manufacturing Company (TSMC). Following widespread industry rumors that TSMC’s production facility for the next generation 3-nanometer chip process could be delayed, Dr. Mark Liu, chairman of TSMC, shared key information about the company’s most recent technology at the event, which Taiwan’s economy minister and other guests attended. The CEO told the audience that the 3-nanometer process is not only a $1.5 trillion product but that its yield rate is also comparable to that of the 5-nanometer process technology.
The celebration of the mass production of a manufacturing process by TSMC took place today for the first time, and it comes as the business deals with a severe industry downturn as well as concerns from Taiwanese critics about whether it intends to leave the country completely. The event was hosted by TSMC in the Tainan area of Taiwan, where it runs two twelve-inch wafers GIGAFABs.
TSMC’s 3nm Technology Has Huge Performance Gains From 5nm Process
The ceremony specifically took place in TSMC’s Fab 18, where it added a new element to the facility used to make 3-nanometer chips. According to Dr. Mark Liu, chairman of TSMC, each of these facilities has a clean room that is 58,000 square meters in size, or double the size of a normal logic foundry.
Furthermore, he claimed that there are no yield issues with the 3-nanometer process, whose yield was higher than the 5-nanometer when it first entered mass production. According to the CEO, the method would produce chips with up to 35% less power consumption and 60% greater logic density than those made using the 5-nanometer manufacturing technology.
Dr. Liu also highlighted that, according to TSMC’s projections, 3-nanometer would manufacture items worth an astounding $1.5 trillion, which was a shocking estimate of the overall value of the new technology as measured by the amount of money its products will be. Although he did not mention it in his address, the duration is five years, according to a TSMC news statement.
Dr. Liu also shared information on the 2-nanometer facilities at TSMC. He claims that they will be constructed in six stages at the scientific parks in Hsinchu and Taichung. Importantly, he emphasized that all plants were proceeding as planned. His remarks were in response to a story from Taiwan’s Economic Daily News that was published early in the morning and stated that the Taichung 2-nanometer facility had been delayed.
The first phase of the fabs is scheduled to start construction next year, and TSMC is targeting 2025 for the production of the next-generation chips.