Intel Designing a Lego Chiplet Architecture For Its Upcoming Generation(s) of CPUs

Intel is working on a new chip stacking technology termed as Foveros, more on that in a bit. This technology will arrive in 3 types, Foveros , Foveros Omni  and Foveros Direct. 

The first type, Foveros will enable high-volume, high-capacity chip production. The second flavour, Foveros Omni allows for 4x interconnect bump density when compared against Intel’s EMIB packaging technology. Lastly, Foveros Direct will increase this lead to around x16 against the first type (Foveros). 

What exactly is Foveros?

To put it simply, Foveros is a chip stacking technology. You can watch this YouTube video from Intel for a visualization. Our chips are made in a monolithic (2D) pattern. Intel thought, ‘What if we stack our chips, vertically’ or in a 3D pattern. This is exactly what Foveros does.

A Visualization for Intel’s Foveros (Top view, not sideways) | Intel

Moore’s Law Lives

Intel’s yet to arrive 14th Gen CPUs will leverage the new 3D Foveros technology in an attempt to continue Moore’s law as long as possible. A disaggregated design results in reduced performance, however, with the 3D stacking technology allowing for much faster interconnects, memory routing and cache will be enhanced. This will enable massive power savings. 

Monolithic vs Disaggregated CPU Design | Intel via Wccftech

In the era of high-speed computing, power is a necessity. However, it should not come at the expense of mass ineffciency. Foveros aims to fix this by reducing the power needed per each bit. As compared to standard packaging, Foveros can reduce power consumption by up to 90%

Standard Packaging vs Foveros | Intel via Wccftech

A Look At the Layout for Meteor Lake

Using Intel’s signature 3D stacking technology, the complete CPU die will be divided into 4 sections. The GPU Tile, SoC Tile, CPU Tile, IO Extended Tile shall power Meteor Lake. These chiplets will be attached (like lego, literally) with one another.

Meteor Lake’s Layout | Intel via Wccftech
  • CPU Tile = Intel 4 ‘7nm’
  • SOC Tile / IOE Tile = TSMC’s 6nm (6N)
  • GPU Tile = TSMC 5nm

A Lego Style Design

The chiplets will be stacked and connected like lego. The die-to-die 36 micrometer pitch will allow for reduced latency and enhanced efficiency. The top and bottom have interconnects for linking with one another. 

Side View of Meteor Lake | Intel via Wccftech

Haswell vs Meteor Lake

For a 10 year performance gap, we see Intel’s Meteor Lake placed neck to neck against Haswell from 2013. The performance difference is not that much (considering it has been 10 years). However, the efficiency increment will be drastic. Besides, actual performance metrics can be as high as 10x

Haswell vs Meteor Lake | Intel via Wccftech

Monolithic Performance with a Disaggregated Design?

Intel claims that Meteor Lake will provide monolithic like power while featuring a disaggregated design. Meteor Lake will have SKUs with TDPs ranging from <10W to >100W. Meteor Lake is planned for 2023, whereas if things go as per plans Arrow Lake can be seen as early as 2024

Meteor Lake Wattage | Intel via Wccftech

Are you excited for Intel’s Meteor Lake? We will see Raptor Lake (13th Gen) first, however, the wait will not be that long. 


Abdullah Faisal

With a love for computers since the age of give, Abdullah has always sought to delve into the depths of information, and uses it as his guiding light. He believes success is of utmost importance as history is written by the victor.
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