Hardware

Intel Takes a Page from ARM’s Playbook, Implements Big.Little With Sunny Cove 10nm Cores

Intel did have significant trouble with their shift to the 10nm node and reports even suggested that the chip company had canned it completely, but we finally received an updated roadmap on Intel’s Architecture Event which helped alleviate some of the concerns. The revised roadmap showcased Sunny Cove which was going to succeed Skylake in 2019 and was indeed on the 10nm node.

Sunny Cove is actually very important for Intel because so far the company has reused old cores on refreshed products which hasn’t really gone down well with the community. Then there’s a persistent threat looming from AMD’s Ryzen and their Zen architecture. AMD has managed to close the performance gap quite significantly on competing products and they have also priced their chips very competitively making Intel’s lineup look bad. This also effects Intel’s server business because AMD will be releasing EPYC Rome Server chips later this year and initial leaks suggest terrific performance. Xeon chips built on the Sunny Cove architecture will definitely help Intel compete in the server space where they have been a dominant force for quite sometime.

Sunny Cove – Intel’s Biggest Microarchitecture Upgrade In Recent Time

Due to delays in 10nm Intel had to stick with 14nm longer than anticipated. This resulted in a lot of refreshed launches, resulting in Kaby Lake, Coffee Lake and Whiskey Lake. There were improvements here and there but nothing too significant. Sunny Cove is finally going to change that.

“Wider” Front End Improvements Source – AnanadTech
“Deeper” Front End Improvements Source – AnandTech

Apart from an increase in raw IPC output there will be general improvements as well. Intel on their Architecture day showcase contextualized the improvements as “Wider” and “Deeper”. Sunny Cove has a larger L1 and L2 cache, also having 5-wide allocations instead of 4. Execution ports are also increased, going from 8 to 10 in Sunny Cove.

IPC Improvement

Intel Lakefield SoC

This SoC will be one of the first products using Sunny Cove cores and also being the first to use Foveros 3D packaging technology. Intel recently revealed more details on their upcoming Lakefield SoC and there’s actually a lot to get excited about.

Basically this is a hybrid CPU using stacking to fit in various parts in a single package.Package-on-package stacking is actually pretty common for mobile SoCs but Intel uses a slightly varied version. Instead of silicon bridges, Foveros tech uses F-T-F microbumps between the stacks. Foveros packaging also allows the components to be placed in different dies. This way Intel can place high performance cores aka the Sunny Cove cores on the more advanced 10nm process, other components can be placed on the 14nm process part of the chip. DRAM layers are placed on top with the CPU and GPU chiplet coming below it and then the base die is placed with cache and I/O.

Another interesting thing here is the implementation of big.LITTLE with x86 hardware. Its basically the use of two types of processors for different types of tasks, the powerful cores are used for resource intensive tasks meanwhile the lower power cores are used for normal functioning. Lakefield uses a five-core design,with four lower power cores (Atom) and one high power core (Sunny Cove). This design is implemented because it improves efficiency as performance is easier to scale between the different core clusters. Lakefield is obviously an SoC aimed towards mobile devices, compact laptops and ultrabooks, but mostly its Intel’s response to Qualcomm who are gearing up to release their own ARM SoCs for Windows devices.


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